Selected Topics of Information Security - Cryptography on Hardware Platforms (WS 2023/24)

Content

Modular_Arithmetic  

This course teaches how to implement cryptographic algorithms efficiently on hardware platforms. It covers hardware implementation aspects of symmetric-key, asymmetric-key cryptographic primitives, true and pseudo random number generation, physically unclonable functions, as well as basics of homomorphic encryption. The content offered in the lectures is accompanied by practical assignments. In the practical assignments, you will be given reference proof-of-concept software implementations and you will build hardware-software codesign architectures for them.

Learning goals:

1. Problem-oriented hardware development for cryptography.
2. Standard and performance-optimized implementation techniques.
3. Secure implementation techniques.
4. Prototyping in real FPGA and performance benchmarking of crypto.

Besides learning how to implement cryptographic algorithms securely and efficiently, you learn design methods for FPGA. In the semiconductor industry, FPGAs are used for prototyping as well as product developments.

Discussions with other students are possible in the #cryptoengineering channel in Discord.

Material

Lecture Slides 00 Introduction and Motivation 01 Introduction to FPGAs 02 Modular Arithmetic-I, Modular Arithmetic-II 03 Design_of_PublicKey_Crypto 04 Random number generation Statistical tests for random numbers Postprocessing of raw TRNG bits 04 Physically Unclonable Function (PUF) 05 AES and its Implementation Aspects 06 FHE Acceleration Practical session/Tutorial slides 00 Introduction 01 Verilog HDL Review 02 Vivado Tutorial, ModelSim Tutorial 03 Vitis Tutorial (Updated)

• Vitis code Tutorial

04 Assignment 2 (Explanation lecture)

• Assignment 2
• Video of Assignment 2 explanation

Example codes: Wrapper for 64-bit multiplier Assignments 01 Assignment 1 - Part 1 (PDF), Assignment 1 - All parts (PDF)

• Python model of Montgomery reduction (for Task-1)
• Python model of NTT-INTT
• Vivado project for the cryptoprocessor, Vitis_code (Updated)

02 Assignment 2 (PDF)

• Vivado project for the cryptoprocessor
• Vitis code

Tools For assignments and practical sessions, we will use Xilinx Vitis/Vivado 2020.2 version (Vitis installation includes Vivado by default). Below, you can find the installation guide for Xilinx Vitis 2020.2.

• Installation guide for Xilinx Vitis/Vivado 2020.2

We will use the PYNQ-Z2 FPGA board for implementing the cryptographic primitives. With Vitis/Vivado 2020.2, you need to copy the PYNQ-Z2 board-specific files into the installation directory (see the installation guide).

• PYNQ-Z2 board files

[See last year's course webpage for an overview.]

Administrative Information

Previous Knowledge Basics of cryptography and digital design (e.g., DSD course). Familiarity with Verilog or SystemVerilog. Prerequisites Curriculum See position in the curriculum Objective After attending this course, students learn how to design cryptographic algorithms on hardware and hardware-software co-design platforms. As a group, students design and implement a cryptoprocessor on an actual FPGA. Language English Teaching Method Lectures will be in-person (2 hours lecture + 1 hour practical session). You will be given two practical assignments and you will work in a team of 2 students in general. How to get a grade Evaluation: 100% from two practical assignments. There will be no written exam. Oral defense after submitting assignments. Registration https://online.tugraz.at/tug_online/ee/rest/pages/slc.tm.cp/course-registration/408162

Lecturers