Zynq UltraScale+ Summary Report
User Configurations
MIO Configurations

CLK Configurations

DDR Configurations

GT Configurations
This design is targeted for xczu9eg board (part number: PROD-2)

Zynq UltraScale+ Design Summary

Device xczu9eg
SpeedGrade -2
Part PROD-2
Description Zynq UltraScale+ PS Configuration Report
Vendor Xilinx

MIO Table View

MIO Pin Peripheral Signal IO Type Speed Pullup Direction Drive Strength(mA)
MIO 0 Quad SPI Flash sclk_out schmitt slow pullup out 12
MIO 1 Quad SPI Flash miso_mo1 schmitt slow pullup inout 12
MIO 2 Quad SPI Flash mo2 schmitt slow pullup inout 12
MIO 3 Quad SPI Flash mo3 schmitt slow pullup inout 12
MIO 4 Quad SPI Flash mosi_mi0 schmitt slow pullup inout 12
MIO 5 Quad SPI Flash n_ss_out schmitt slow pullup out 12
MIO 6 Feedback Clk clk_for_lpbk schmitt slow pullup out 12
MIO 7 Quad SPI Flash n_ss_out_upper schmitt slow pullup out 12
MIO 8 Quad SPI Flash mo_upper[0] schmitt slow pullup inout 12
MIO 9 Quad SPI Flash mo_upper[1] schmitt slow pullup inout 12
MIO 10 Quad SPI Flash mo_upper[2] schmitt slow pullup inout 12
MIO 11 Quad SPI Flash mo_upper[3] schmitt slow pullup inout 12
MIO 12 Quad SPI Flash sclk_out_upper schmitt slow pullup out 12
MIO 13 GPIO0 MIO gpio0[13] schmitt slow pullup inout 12
MIO 14 I2C 0 scl_out schmitt slow pullup inout 12
MIO 15 I2C 0 sda_out schmitt slow pullup inout 12
MIO 16 I2C 1 scl_out schmitt slow pullup inout 12
MIO 17 I2C 1 sda_out schmitt slow pullup inout 12
MIO 18 UART 0 rxd schmitt slow pullup in 12
MIO 19 UART 0 txd schmitt slow pullup out 12
MIO 20 UART 1 txd schmitt slow pullup out 12
MIO 21 UART 1 rxd schmitt slow pullup in 12
MIO 22 GPIO0 MIO gpio0[22] schmitt slow pullup inout 12
MIO 23 GPIO0 MIO gpio0[23] schmitt slow pullup inout 12
MIO 24 CAN 1 phy_tx schmitt slow pullup out 12
MIO 25 CAN 1 phy_rx schmitt slow pullup in 12
MIO 26 GPIO1 MIO gpio1[26] schmitt slow pullup inout 12
MIO 27 DPAUX dp_aux_data_out schmitt slow pullup out 12
MIO 28 DPAUX dp_hot_plug_detect schmitt slow pullup in 12
MIO 29 DPAUX dp_aux_data_oe schmitt slow pullup out 12
MIO 30 DPAUX dp_aux_data_in schmitt slow pullup in 12
MIO 31 PCIE reset_n schmitt slow pullup out 12
MIO 32 PMU GPO 0 gpo[0] schmitt slow pullup out 12
MIO 33 PMU GPO 1 gpo[1] schmitt slow pullup out 12
MIO 34 PMU GPO 2 gpo[2] schmitt slow pullup out 12
MIO 35 PMU GPO 3 gpo[3] schmitt slow pullup out 12
MIO 36 PMU GPO 4 gpo[4] schmitt slow pullup out 12
MIO 37 PMU GPO 5 gpo[5] schmitt slow pullup out 12
MIO 38 GPIO1 MIO gpio1[38] schmitt slow pullup inout 12
MIO 39 SD 1 sdio1_data_out[4] schmitt slow pullup inout 12
MIO 40 SD 1 sdio1_data_out[5] schmitt slow pullup inout 12
MIO 41 SD 1 sdio1_data_out[6] schmitt slow pullup inout 12
MIO 42 SD 1 sdio1_data_out[7] schmitt slow pullup inout 12
MIO 43 GPIO1 MIO gpio1[43] schmitt slow pullup inout 12
MIO 44 SD 1 sdio1_wp schmitt slow pullup in 12
MIO 45 SD 1 sdio1_cd_n schmitt slow pullup in 12
MIO 46 SD 1 sdio1_data_out[0] schmitt slow pullup inout 12
MIO 47 SD 1 sdio1_data_out[1] schmitt slow pullup inout 12
MIO 48 SD 1 sdio1_data_out[2] schmitt slow pullup inout 12
MIO 49 SD 1 sdio1_data_out[3] schmitt slow pullup inout 12
MIO 50 SD 1 sdio1_cmd_out schmitt slow pullup inout 12
MIO 51 SD 1 sdio1_clk_out schmitt slow pullup out 12
MIO 52 USB 0 ulpi_clk_in schmitt slow pullup in 12
MIO 53 USB 0 ulpi_dir schmitt slow pullup in 12
MIO 54 USB 0 ulpi_tx_data[2] schmitt slow pullup inout 12
MIO 55 USB 0 ulpi_nxt schmitt slow pullup in 12
MIO 56 USB 0 ulpi_tx_data[0] schmitt slow pullup inout 12
MIO 57 USB 0 ulpi_tx_data[1] schmitt slow pullup inout 12
MIO 58 USB 0 ulpi_stp schmitt slow pullup out 12
MIO 59 USB 0 ulpi_tx_data[3] schmitt slow pullup inout 12
MIO 60 USB 0 ulpi_tx_data[4] schmitt slow pullup inout 12
MIO 61 USB 0 ulpi_tx_data[5] schmitt slow pullup inout 12
MIO 62 USB 0 ulpi_tx_data[6] schmitt slow pullup inout 12
MIO 63 USB 0 ulpi_tx_data[7] schmitt slow pullup inout 12
MIO 64 Gem 3 rgmii_tx_clk schmitt slow pullup out 12
MIO 65 Gem 3 rgmii_txd[0] schmitt slow pullup out 12
MIO 66 Gem 3 rgmii_txd[1] schmitt slow pullup out 12
MIO 67 Gem 3 rgmii_txd[2] schmitt slow pullup out 12
MIO 68 Gem 3 rgmii_txd[3] schmitt slow pullup out 12
MIO 69 Gem 3 rgmii_tx_ctl schmitt slow pullup out 12
MIO 70 Gem 3 rgmii_rx_clk schmitt slow pullup in 12
MIO 71 Gem 3 rgmii_rxd[0] schmitt slow pullup in 12
MIO 72 Gem 3 rgmii_rxd[1] schmitt slow pullup in 12
MIO 73 Gem 3 rgmii_rxd[2] schmitt slow pullup in 12
MIO 74 Gem 3 rgmii_rxd[3] schmitt slow pullup in 12
MIO 75 Gem 3 rgmii_rx_ctl schmitt slow pullup in 12
MIO 76 MDIO 3 gem3_mdc schmitt slow pullup out 12
MIO 77 MDIO 3 gem3_mdio_out schmitt slow pullup inout 12

PS Clocks information

PSS REF CLK : 33.330
Name Source Input Frequency (MHz)
APLL PSS_REF_CLK 2399.760
DPLL PSS_REF_CLK 2133.120
VPLL PSS_REF_CLK 2999.700
RPLL PSS_REF_CLK 1499.850
IOPLL PSS_REF_CLK 2999.700

Peripheral Requested Frequency (MHz) Source Actual Frequency (MHz)
GEM3 freq (MHz) 125 IOPLL 124.987500
USB0 freq (MHz) 250 IOPLL 249.975000
QSPI freq (MHz) 125 IOPLL 124.987500
SDIO1 freq (MHz) 200 IOPLL 187.481250
UART0 freq (MHz) 100 IOPLL 99.990000
UART1 freq (MHz) 100 IOPLL 99.990000
I2C0 freq (MHz) 100 IOPLL 99.990000
I2C1 freq (MHz) 100 IOPLL 99.990000
CAN1 freq (MHz) 100 IOPLL 99.990000
CPU_R5 freq (MHz) 500 IOPLL 499.950000
IOU_SWITCH freq (MHz) 250 IOPLL 249.975000
LPD_SWITCH freq (MHz) 500 IOPLL 499.950000
LPD_LSBUS freq (MHz) 100 IOPLL 99.990000
GEM_TSU freq (MHz) 250 IOPLL 249.975000
TIMESTAMP freq (MHz) 100 IOPLL 99.990000
PSU__CRL_APB__USB3_REF_CTRL__freqmhz 20 IOPLL 19.998000
PCAP freq (MHz) 200 IOPLL 187.481250
DBG_LPD freq (MHz) 250 IOPLL 249.975000
ADMA freq (MHz) 500 IOPLL 499.950000
PL0 freq (MHz) 100 IOPLL 99.990000
AMS freq (MHz) 50 IOPLL 49.995000
ACPU freq (MHz) 1200 APLL 1199.880000
DBG FPD freq (MHz) 250 IOPLL 249.975000
DP VIDEO freq (MHz) 300 VPLL 299.970000
DP AUDIO freq (MHz) 25 RPLL 24.997500
DP STC freq (MHz) 27 RPLL 26.783036
SATA freq (MHz) 250 IOPLL 249.975000
PCIE freq (MHz) 250 IOPLL 249.975000
DDR_CTRL freq MHz) 533.500 DPLL 533.280000
GPU freq (MHz) 500 IOPLL 499.950000
GDMA freq (MHz) 600 APLL 599.940000
DPDMA freq (MHz) 600 APLL 599.940000
TOPSW_MAIN freq (MHz) 533.33 DPLL 533.280000
TOPSW_LSBUS freq (MHz) 100 IOPLL 99.990000
DBG TSTMP freq (MHz) 250 IOPLL 249.975000

DDR Memory information

Parameter name Value Description
ENABLE 1 Enable the PS DDR Controller
DDR Interface freq (MHz) 1067 --
MEMORY TYPE DDR 4 Type of memory interface
DM DBI UDIMM
BUS WIDTH 64 Bit Data width of DDR interface, not including ECC data width
ECC Disabled Enables error correction code support
SPEED BIN DDR4_2133P Speed Bin
CL 15 Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL 14 CAS write latency setting in memory clock cycles
DDR AL 0 Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD 15 tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP 15 Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC 47.06 Row cycle time (ns)
T RAS MIN 33 Minimum number of memory clock cycles required between an Active and Precharge command
T FAW 30.0 Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH 8 Bits Width of individual DRAM components
DEVICE CAPACITY 4096 MBits Storage capacity of individual DRAM components
BG ADDR COUNT 2 Number of bank group address pins
RANK ADDR COUNT 0 Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT 2 Number of bank address pins
ROW ADDR COUNT 15 Number of row address pins
COL ADDR COUNT 10 Number of column address bits
C_DDR_RAM_HIGHADDR 0xFFFFFFFF --

GT lanes information

Protocol GT lane# Ref Clk Sel Ref freq (MHz)
PCIe GT Lane0 Ref Clk0 100
DP GT Lane1 Ref Clk3 27
USB0 GT Lane2 Ref Clk2 26
SATA GT Lane3 Ref Clk1 125