Content
The course is about the programming and design of integrated systems, with a strong focus on System-On-Chip (SoC) design. We will gather practical hands-on experience by programming our own FPGAs and designing secure multi-media systems. We will investigate:
- What are SoCs and where are they used today?
- How can we design SW and HW for SoCs?
- How do SoCs communicate with their environment?
Additionally to these core questions, we will cover security and safety aspects of such systems.
Material
Assignments
Pitfalls and FAQ
- What is the proper way to modify/update an IP block, e.g., add more functionality to it? Open the block design in Vivado, then right click your IP core and select “Edit in IP packager”
- Make sure to use a working USB cable. There are cables which are not intended for data transmission, only for charging the device.
- Carefully read the log output of your device while booting Linux when you think there is an error.
- “Unable to read file system-top.dtb”: adapt your defconfig file accordingly. If your device tree blob is called “katze123.”, then the defconfig file must also be changed to use “katze123.***” as the name of the device tree, and hence, uenv.txt must contain “devicetree_image=katze123.dtb”. The same holds for all other files.
- To find possible problems with your design, have a look at the logs in Vivado (especially the Critical Warnings).
- Helpful for your device driver: platform_get_resource, ioremap
- When using gparted for formatting the SD card, make sure the partitioning system of the first partition is set to msdos instead of gpt.
- Buildroot does not rebuild your driver even though the source changed? Run make packagename-dirclean before make.
- Buildroot (cmake) says “The CXX compiler identification is unknown” and you cannot build your C++ module: double-check your GCC version! You can do this in the menuconfig (Toolchain / GCC compiler version)
- Working with the AXI VIP: “import axi_vip_pkg::*;” and “import design_1_axi_vip_0_0_pkg::*;” have red squiggles underneath them, hover says “‘axi_vip_pkg’ is not declared”, simulation fails with error (“[VRFC 10-2991] ‘IF’ is not declared under prefix ‘inst’ for the line where the master agent is created.”) – try to clean all build artefacts (ie reset all synthesis/design runs, or try to create a new project. If this doesn’t help, reinstall Vivado)
Administrative Information
| 8.11. |
Topic #1: ASIC vs FPGAs |
Slides |
| 8.11. |
Topic #3: The FPGA design process |
Slides |
| 8.11. |
Topic #5: ARM AXI Interface |
Slides |
| 22.11. |
Topic #6: Network-on-Chip (NoC) designs |
Slides |
| 22.11. |
Topic #7: Weak point bitstream? |
Slides |
| 29.11. |
Topic #8: FPGA Bitstream Encryption |
Slides |
| 29.11. |
Topic #9: Remote Power Attacks on FPGAs |
Slides |
| 29.11. |
Topic #10: Fault attacks on FPGAs |
Slides |
| 6.12. |
Topic #11: EM Side-Channel Attacks on SoCs |
Slides |
| 6.12. |
Topic #14: Reverse Engineering ICs |
Slides |
| 13.12. |
Topic #15: Security Co-Processors |
Slides |
| 13.12. |
Topic #13: Hardware Trojan Attacks in FPGAs |
Slides |
| 10.1. |
Topic #18: Formal Verification in Hardware Design |
Slides |
| 10.1. |
Topic #19: High Level Synthesis |
Slides |
| 17.1. |
Topic #21: Open-Source Hardware |
Slides |
| 24.1. |
Topic #24: Booting Linux |
Slides |
| 24.1. |
Topic #26: FPGAs and Neural Networks / ZynqNet |
Slides |
| 24.1. |
Topic #20: FPGAs in Space |
Slides |
