Digital System Design (SS 2024)

Course Number 705044 | Sommersemester 2024

Content

The goal of the course Digital System Design is to teach the central aspects of designing digital integrated circuits by a systematic approach and methodology. The course covers the whole spectrum of the design: it starts with specifications on system-level and ends at the generation and verification of layout masks, which are needed for production. The content offered in the lectures is accompanied by a lab exercise where participants have the chance to put the knowledge into practice by using the latest professional design tools as they are used in the semiconductor industry.

The practical lab of Digital System Design covers the design of a digital integrated circuit. During the work the following tasks have to be accomplished:

  • System-level specification
  • Algorithmic evaluation
  • Architectural choices
  • Register-level transfer modeling (VHDL, Verilog, SystemVerilog)
  • Dynamic functional verification (HDL simulation)
  • Synthesis
  • Place & Route
  • Back-end verification

The practical work is committed with either open-source tools (OpenROAD, Caravel Harness SoC) or professional CAD tools from Cadence. The outcome of the lab is the layout of a CMOS circuit that is nearly suitable for tape-out (production).

You can find last year's DSD course here: SS2023

Material

Topic Slides
01 Introduction & Motivation Download
02 Digital Design Flow | Cipher Spec Download      CipherSpec
03 Architectural Design Methodology Part 1 Download
04 Architectural Design Methodology Part 1 (continuation)
05 Architectural Design and Design Methodology Part 2 Download
06 Architectural Design Methodology Part 2 (continuation)
07 Architecture design Example Download
08 Synchronous Design and Clocking Download
09 CMOS Gates and Design for Low-Power Download
10 Backend Design
11 Verification and Validation
Course Intro: Crypto on Hardware
Sample questions for Architecture Design part only

Administrative Information

Lecture

Exam. There is one written exam at the end of the semester. An additional exam date is planned for the end of September. Other exam dates are offered on request.

Practicals

Practicals: In the lab practicals, students design an integrated digital circuit that implements a cryptographic algorithm. By applying a hierarchical structuring of the circuit, many principles of digital system design become clear. The lab centers on the description of circuits using hardware-description languages but it also covers algorithmic improvements and optimizations on circuit level.

Groups. The Digital System Design KU is done in groups of two. Look out for a group early.

Computers, Accounts, Software, Design flow. For the duration of the practicals, participants have access to the research cluster located at IAIK via a studentnet account.

Discord. Discussions with other students are possible in the #dsd channel in Discord.

Exams. The practicals is a team work of two students. The final submission of deliverables is graded during a colloquium / discussion.

Topic Download
Cadence Software Usage Agreement Download
Design Document Draft Download
SystemVerilog Tutorial (Legacy) Download
IAIK-Open-Flow Presentation Download
IAIK-Closed-Flow Presentation Download
Assignment Sheet Download
Assignment 1 presentation Download
Assignment 2 presentation Download

Lecture Dates

Date Begin End Location Event Type Comment
2024/05/22 08:30 10:00 Seminarraum Abhaltung KU fix/
2024/05/28 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2024/05/29 08:30 10:00 Seminarraum Abhaltung KU fix/
2024/06/04 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2024/06/05 08:30 10:00 Seminarraum Abhaltung KU fix/
2024/06/11 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2024/06/12 08:30 10:00 Seminarraum Abhaltung KU fix/
2024/06/18 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2024/06/19 08:30 10:00 Seminarraum Abhaltung KU fix/
2024/06/25 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/

Lecturers

Sujoy Sinha Roy
Sujoy
Sinha Roy

Assistant Professor

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Florian Hirner
Florian
Hirner

PhD Student

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Moritz Waser
Moritz
Waser

PhD Student

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