Digital System Design (SS 2023)

Course Number 705044 and 705045 | Sommersemester 2023

Lecturers

Sujoy Sinha Roy

Pascal Nasahl

Teaching Assistants

Patrick Schuster

Content

The goal of the course Digital System Design is to teach the central aspects of designing digital integrated circuits by a systematic approach and methodology. The course covers the whole spectrum of the design: it starts with specifications on system-level and ends at the generation and verification of layout masks, which are needed for production. The content offered in the lectures is accompanied by a lab exercise where participants have the chance to put the knowledge into practice by using the latest professional design tools as they are used in the semiconductor industry.

The practical lab of Digital System Design covers the design of a digital integrated circuit. During the work the following tasks have to be accomplished:

  • System-level specification
  • Algorithmic evaluation
  • Architectural choices
  • Register-level transfer modeling (VHDL, Verilog, System Verilog)
  • Dynamic functional verification (HDL simulation)
  • Synthesis
  • Place & Route
  • Back-end verification

The practical work is committed with professional CAD tools – mostly from Cadence that are used in industry too. The outcome of the lab is the layout of a CMOS circuit that is nearly suitable for tape-out (production).

Material

Topic Slides
01 Introduction & Motivation Download
02 Digital Design Flow | Cipher Spec Download  Cipher_specification
03 HDL Introduction, Verilog Tutorial Part 1 VerilogHDL
04 Verilog Tutorial Part 2
05 Architectural Design and Design Methodology Part 1
06 Architectural Design and Design Methodology Part 2
07 Testing and Verification
08 Formal Verification for Hardware Designs
09 Synchronous Design and Clocking
10 Backend Design
11 CMOS Gates and Design for Low-Power

Administrative Information

Lecture

Exam. There is one written exam at the end of the semester. An additional exam date is planned for the end of September. Other exam dates are offered on request.

Practicals

Practicals: In the lab practicals, students design an integrated digital circuit that implements a cryptographic algorithm. By applying a hierarchical structuring of the circuit, many principles of digital system design become clear. The lab centers on the description of circuits using hardware-description languages but it also covers algorithmic improvements and optimizations on circuit level.

Groups. The Digital System Design KU is done in groups of two. Look out for a group early.

Computers, Accounts, Software, Design flow. For the duration of the practicals, participants have access to the research cluster located at IAIK via a studentnet account.

Discord. Discussions with other students are possible in the #dsd channel in Discord.

Exams. The practicals is a team work of two students. The final submission of deliverables is graded during a colloquium / discussion.

Topic Download
Cadence Software Usage Agreement Download
Design Document Draft Download
IAIK design-flow presentation Download
IAIK design-flow video tutorial Download
Assignment Sheet Download
Assignment 1 presentation Download
Assignment 2 presentation

Lecture Dates

Date Begin End Location Event Type Comment
2023/03/28 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2023/03/28 11:30 12:30 HS i3 "LENZING Hörsaal" Abhaltung KU fix/
2023/04/18 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2023/04/25 09:15 10:00 Seminarraum Abhaltung KU fix/
2023/04/25 09:15 10:00 Seminarraum Abhaltung KU fix/
2023/04/25 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2023/05/02 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2023/05/09 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2023/05/16 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2023/05/23 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2023/06/06 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2023/06/13 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2023/06/20 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2023/06/27 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/
2023/06/27 10:00 11:30 HS i3 "LENZING Hörsaal" Abhaltung VO fix/

Lecturers

Sujoy Sinha Roy
Sujoy
Sinha Roy

Assistant Professor

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Pascal Nasahl
Pascal
Nasahl

PhD Student

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Teaching Assistants

Patrick Schuster
Patrick
Schuster


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