Stefan Steinegger

Dipl.-Ing. BSc

Secure Systems, PhD Student

Stefan Steinegger is a PhD student of Stefan Mangard in the Secure Systems (SESYS) group at the Institute of Applied Information Processing and Communications (IAIK) in Graz, Austria. He graduated to Dipl.Ing. (MSc) from the University of Technology Graz in 2018. His master's thesis is about power side-channel attacks and defenses for hardware implementations of a cryptographic scheme called BLISS.
Stefan Steinegger


My research interests include secure processor designs in Hard- and Software for RISC-V as well as side-channel attacks and defenses.


I teach a graduate course that focuses on designing and implementing hardware and software for embedded systems with focus on a different topic each year.

  • System-on-Chip Architectures and Modelling (lecture: winter term)


A Fast and Compact RISC-V Accelerator for Ascon and Friends

Steinegger S., Primas R.
Smart Card Research and Advanced Applications - 19th International Conference, CARDIS 2020, Revised Selected Papers, 19th International Conference, CARDIS 2020, Virtual Event, November 18–19, 2020, Revised Selected Papers, CARDIS 2020, 53-67, (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 12609 LNCS)

Donky: Domain Keys – Efficient In-Process Isolation for RISC-V and x86

Schrammel D., Weiser S., Steinegger S., Schwarzl M., Schwarz M., Mangard S., Gruß D.
Proceedings of the 29th USENIX Security Symposium, 29th USENIX Security Symposium, 1677-1694, (Proceedings of the 29th USENIX Security Symposium

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