Digital System Integration and Programming (WS 2021/22)

Course Number 705007 | Wintersemester 2021/22

Content

The course is about the programming and design of integrated systems, with a strong focus on System-On-Chip (SoC) design. We will gather practical hands-on experience by programming our own FPGAs and designing secure multi-media systems. We will investigate:

  • What are SoCs and where are they used today?
  • How can we design SW and HW for SoCs?
  • How do SoCs communicate with their environment?

Additionally to these core questions, we will cover security and safety aspects of such systems.

Material

 

 

Assignments
Pitfalls and FAQ
  • What is the proper way to modify/update an IP block, e.g., add more functionality to it? Open the block design in Vivado, then right click your IP core and select “Edit in IP packager”
  • Make sure to use the correct USB cable. There are cables which are not intended for data transmission, only for charging the device.
  • Carefully read the log output of your device while booting Linux when you think there is an error.
    • “Unable to read file system-top.dtb”: adapt your defconfig file accordingly. If your device tree blob is called “katze123.”, then the defconfig file must also be changed to use “katze123.***” as the name of the device tree, and hence, uenv.txt must contain “devicetree_image=katze123.dtb”. The same holds for all other files.
  • To find possible problems with your design, have a look at the logs in Vivado (especially the Critical Warnings).
  • Helpful for your device driver: platform_get_resource, ioremap
  • When using gparted for formatting the SD card, make sure the partitioning system of the first partition is set to msdos instead of gpt.
  • Buildroot does not rebuild your driver even though the source changed? Run make packagename-dirclean before make.
  • Buildroot (cmake) says “The CXX compiler identification is unknown” and you cannot build your C++ module: double-check your GCC version! You can do this in the menuconfig (Toolchain / GCC compiler version)
  • Working with the AXI VIP: “import axi_vip_pkg::*;” and “import design_1_axi_vip_0_0_pkg::*;” have red squiggles underneath them, hover says “‘axi_vip_pkg’ is not declared”, simulation fails with error (“[VRFC 10-2991] ‘IF’ is not declared under prefix ‘inst’ for the line where the master agent is created.”) – try to clean all build artefacts (ie reset all synthesis/design runs, or try to create a new project. If this doesn’t help, reinstall Vivado)

Administrative Information

Seminar Presentations
27.10. SoC Basics Architecture of FPGAs Slides
27.10. SoC Basics ARM AXI Interface Slides
3.11. SoC Basics Alternative SoC Bus Interconnections Slides
3.11. SoC Security FPGA Bitstream Encryption Basics Slides
10.11. SoC Security FPGA Bitstream Encryption Vulnerabilities Slides
17.11.13.1. SoC Security Hardware Trojan Attacks in FPGAs
17.11. SoC Security TEEs and Enclaves Slides
24.11. SoC Environment Booting Linux Slides
1.12. SoC Environment Design of Mixed-Signal SoCs Slides
1.12. SoC Environment Soft Cores and ARM/RISC-V Processors Slides
15.12. SoC Environment FPGAs and Neural Networks / ZynqNet Slides
15.12. SoC Environment FPGAs in Space Slides

Lecture Dates

Date Begin End Location Event Type Comment
2022/01/26 10:00 12:00 External Location (please check TUGRAZonline) Abhaltung VU fix/Discord

Lecturers

Barbara Gigerl
Barbara
Gigerl

PhD Student

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