Digital System Design

Course Number 705044 and 705045 | Sommersemester 2020

Content

Goal of the course Digital System Design is to teach the central aspects of designing digital integrated circuits by a systematic approach and methodology. The course covers the whole spectrum of the design: it starts with specifications on system level and ends at the generation and verification of layout masks, which are needed for production. The content offered in the lectures is accompanied by a lab exercise where participants have the chance to put the knowledge into practice by using the latest professional design tools as they are used in semiconductor industry.

The lecture notes are available as PDF documents and show one slide per page.

Topic Download
01 Introduction & Motivation https://teaching.iaik.tugraz.at/_media/dsd/01_introduction.pdf
02 RTL Design and HDL Introduction https://teaching.iaik.tugraz.at/_media/dsd/02_hdlmodelling.pdf
03 Digital Design Flow https://teaching.iaik.tugraz.at/_media/dsd/03_designflow.pdf
04 Architectural Design and Design Methodology https://teaching.iaik.tugraz.at/_media/dsd/04_designmethodology_architecture.pdf
05 Testing and Verification https://teaching.iaik.tugraz.at/_media/dsd/05_testing_verification_and_validation.pdf
06 Formal Verification for Hardware Designs https://teaching.iaik.tugraz.at/_media/dsd/06_formal_verification.pdf
07 Side-Channel Analysis and Countermeasures https://teaching.iaik.tugraz.at/_media/dsd/07_masking_sca.pdf
08 Fault Attacks and Countermeasures https://teaching.iaik.tugraz.at/_media/dsd/08_faults.pdf
09 Synchronous Design and Clocking https://teaching.iaik.tugraz.at/_media/dsd/09_clocking.pdf
10 CMOS Gates and Design for Low-Power https://teaching.iaik.tugraz.at/_media/dsd/10_cmos_and_design_for_low_power.pdf
11 Backend Design https://teaching.iaik.tugraz.at/_media/dsd/11_backend.pdf

The practical lab of Digital System Design covers the design of a digital integrated circuit. During the work the following tasks have to be accomplished:

  • System-level specification
  • Algorithmic evaluation
  • Architectural choices
  • Register-level transfer modelling (VHDL, Verilog, System Verilog)
  • Dynamic functional verification (HDL simulation)
  • Synthesis
  • Place & Route
  • Back-end verification

The practical work is committed with professional CAD tools – mostley from Cadence that are used in industry too. The outcome of the lab is the layout of a CMOS circuit that is nearly suitable for tape-out (production).

Administrative Information

Groups. The Digital System Design KU is done in groups of two. Look out for a group early. Computers, Accounts, Software, Design flow. For the duration of the practicals, participants have access to the research cluster located at IAIK via a studentnet account.

Communication. Relevant info about the practicals will be published in the Newsgroup tu-graz.lv.vlsi-design. Please monitor this newsgroup throughout the semester. Questions and discussions are welcome there.

Exams. The practicals is a team work of two students. The final submission of deliverables is graded during a colloquium / discussion.

Practicals: In the lab practicals, students design an integrated digital circuit that implements an algorithm with relevance in digital communications. By applying a hierarchical structuring of the circuit, many principles of digital system design become clear. The lab centers on the description of circuits using hardware-description languages but it also covers algorithmic improvements and optimizations on circuit level.

Lecture Dates

Date Begin End Location Event Type Comment
2020/03/03 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/03/10 08:45 10:45 Seminarraum Abhaltung KU fix/
2020/03/10 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/03/17 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/03/24 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/03/31 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/04/21 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/04/28 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/04/28 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/05/05 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/05/12 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/05/19 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/05/26 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/06/09 09:15 10:45 Seminarraum Abhaltung VO fix/
2020/06/16 08:30 10:45 Seminarraum Abhaltung KU fix/
2020/06/16 08:30 10:45 Seminarraum Abhaltung KU fix/
2020/06/16 09:15 10:45 Seminarraum Abhaltung VO fix/

Lecturers

Robert Schilling
Robert
Schilling

PhD Candidate

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