Digital System Design
Table of Content
Goal of the course Digital System Design is to teach the central aspects of designing digital integrated circuits by a systematic approach and methodology. The course covers the whole spectrum of the design: it starts with specifications on system level and ends at the generation and verification of layout masks, which are needed for production. The content offered in the lectures is accompanied by a lab exercise where participants have the chance to put the knowledge into practice by using the latest professional design tools as they are used in semiconductor industry.
The lecture notes are available as PDF documents and show one slide per page.
|01 Introduction & Motivation||Download|
|02 Processor Design||Download|
|03a HDL Introduction, Verilog Tutorial||Download||Download|
|03b Verilog Tutorial Part 2||Download||Download|
|04 Digital Design Flow||Download||Download|
|05 Architectural Design and Design Methodology||Download||Download|
|06 Testing and Verification||Download||Download|
|07 Formal Verification for Hardware Designs||Download||Download|
|08 Side-Channel Analysis and Fault Attacks||Download||Download|
|09 Synchronous Design and Clocking||Download||Download|
|10 CMOS Gates and Design for Low-Power||Download||Download|
|11 Backend Design||Download||Download|
The practical lab of Digital System Design covers the design of a digital integrated circuit. During the work the following tasks have to be accomplished:
- System-level specification
- Algorithmic evaluation
- Architectural choices
- Register-level transfer modelling (VHDL, Verilog, System Verilog)
- Dynamic functional verification (HDL simulation)
- Place & Route
- Back-end verification
The practical work is committed with professional CAD tools – mostly from Cadence that are used in industry too. The outcome of the lab is the layout of a CMOS circuit that is nearly suitable for tape-out (production).
Groups. The Digital System Design KU is done in groups of two. Look out for a group early.
Computers, Accounts, Software, Design flow. For the duration of the practicals, participants have access to the research cluster located at IAIK via a studentnet account.
Communication. Relevant info about the practicals will be published in the Newsgroup tu-graz.lv.vlsi-design. Please monitor this newsgroup throughout the semester. Questions and discussions are welcome there.
Exams. The practicals is a team work of two students. The final submission of deliverables is graded during a colloquium / discussion.
Practicals: In the lab practicals, students design an integrated digital circuit that implements an algorithm with relevance in digital communications. By applying a hierarchical structuring of the circuit, many principles of digital system design become clear. The lab centers on the description of circuits using hardware-description languages but it also covers algorithmic improvements and optimizations on circuit level.
|Cadence Software Usage Agreement||Download|
|Assignment presentation for SS2020||Download|
|Design Document Draft||Download|
|IAIK design-flow presentation||Download|
|Assignment 1 presentation||Download|