Computer Organization and Networks (WS 2021/22)

Course Number INB06000UF | Wintersemester 2021/22

From a single gate to a web server in one semester


In this course we study logic design and computer organization. We learn to model synchronous digital systems at functional layer as well as structural layer by using the hardware-design language Verilog. Based on this, we discuss typical concepts found in computer organization: The fetch/execute algorithm, instruction sets, input and output, the stack, interrupt, handshake, memory technologies, direct memory access, and virtual memory. Furthermore, we learn the fundamentals of computer networks and communication technology. It discusses the network layers typically found in today's Internet-based communication. Thus, protocols found in today's networks are analyzed with respect to their function and their historical development.

The course is offered for students in the third semester within their bachelor studies. It is advisable to have successfully completed the programming courses offered in the first and second semesters. The course consists of four parts:

  • Basics (logic gates, number representation, sequential logic, state machines)
  • Processors, part I (Instruction sets, pipelining, memory layout, peripherals, C to machine language, interrupts)
  • Networks (Basics, Layers: Link, network, transport and application)
  • Processors, part II (branch prediction, security)


Lecture Recordings are available on TUbe. All examples that are shown in the lectures are available via git from examples-2021.
Date Begin End Slides
2021-10-06 13:00 15:15 00 Welcome 01 Combinational Circuits
2021-10-13 13:00 15:15 02 Number representation
2021-10-20 13:00 15:15 03 State Machines
2021-10-27 13:00 15:15 04 Basics on processors
2021-11-03 13:00 15:15 05 Pipelining
2021-11-10 13:00 15:15 06a Assembly, Stack & Calling Convention
2021-11-17 13:00 15:15 06a continued 06b Stack examples
2021-11-24 13:00 15:15 07 Network basics, link layer, and network layer
2021-12-09 17:30 19:45 08 Network and transport layer
2020-12-15 13:00 15:15 09 Application layer + Networking wrap-up
2021-01-12 13:00 15:15 10_Polling and Interrupts 11_Faster Processors
2021-01-19 13:00 15:15 Second Part (Caches) of Chapter 11
2021-01-26 13:00 15:15 12 Virtual Memory 13 Information on Exam
Date Event
2021-10-08 publication Task 1 tutorial videos: Getting started, Task 1.a, SystemVerilog, Task 1.b
2021-10-11 weekly question hours start
2021-10-29 deadline Task 1.a
2021-11-05 deadline Task 1.b publication Task 2 tutorial videos: Task 2.a, Task 2.b
2021-11-26 deadline Task 2.a
2021-12-03 deadline Task 2.b publication Task 3 tutorial videos: Task 3.a (slides), Task 3.b (slides, examples)
2021-12-06 week of assignment interviews for Tasks {1.a, 1.b, 2.a}
2022-01-14 deadline Task 3.a
2022-01-21 deadline Task 3.b weekly question hours end
2022-01-24 start assignment interviews for Tasks {2.b, 3.a, 3.b}
Lecture exams
  • 30th of May 2022
  • 23rd of June 2022
Material of Previous Years

Administrative Information

The lecture will be held in a hybrid setting. The practicals will be held online.
  • The lecture takes place every Wednesday at 13:00 and will be held in two blocks of 60min with a 15min break in-between. The exam after the annual lecture is in written form with a duration of 90 minutes.
    • “lecture hall group”: show up on Wednesday at 13:00 in lecture hall i13. A valid 3G certificate is required.
    • “Standardgruppe”: join the live lecture on Wednesday at 13:00 at TUTube to participate. Questions in the chat will be forwarded to the lecturer.
  • The practicals consist of these parts:
    • tutorial videos: will be published here to introduce students to a topic or assignment
    • question hours: happen every week. Time and day varies among TAs.
    • assignment sheet: will contain the assignments and is distributed with your git repository at the beginning of the semester
    • deadlines: always happen on 23:59
    • assignment interviews: your TA will send you an invitation. You discuss your solutions with your TA in Discord then.
    • grading: based on the assignments handed in by your TA.


Stefan Mangard

Head of Institute

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Jakob Heher

PhD Student

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Martin Unterguggenberger

PhD Student

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Moritz Waser

PhD Student

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