Digital System Integration and Programming (WS 2022/23)

Content

The course is about the programming and design of integrated systems, with a strong focus on System-On-Chip (SoC) design. We will gather practical hands-on experience by programming our own FPGAs and designing secure multi-media systems. We will investigate:

• What are SoCs and where are they used today?
• How can we design SW and HW for SoCs?
• How do SoCs communicate with their environment?

Additionally to these core questions, we will cover security and safety aspects of such systems.

Pitfalls and FAQ

• What is the proper way to modify/update an IP block, e.g., add more functionality to it? Open the block design in Vivado, then right click your IP core and select "Edit in IP packager"
• Make sure to use a correct USB cable. There are cables which are not intended for data transmission, only for charging the device.
• Carefully read the log output of your device while booting Linux when you think there is an error. "Unable to read file system-top.dtb": adapt your defconfig file accordingly. If your device tree blob is called "katze123.", then the defconfig file must also be changed to use "katze123.***" as the name of the device tree, and hence, uenv.txt must contain "devicetree_image=katze123.dtb". The same holds for all other files.
• To find possible problems with your design, have a look at the logs in Vivado (especially the Critical Warnings).
• Helpful for your device driver: platform_get_resource, ioremap
• When using gparted for formatting the SD card, make sure the partitioning system of the first partition is set to msdos instead of gpt.
• Buildroot does not rebuild your driver even though the source changed? Run make packagename-dirclean before make.
• Buildroot (cmake) says "The CXX compiler identification is unknown" and you cannot build your C++ module: double-check your GCC version! You can do this in the menuconfig (Toolchain / GCC compiler version)
• Working with the AXI VIP: "import axi_vip_pkg::*;" and "import design_1_axi_vip_0_0_pkg::*;" have red squiggles underneath them, hover says "‘axi_vip_pkg’ is not declared", simulation fails with error ("[VRFC 10-2991] ‘IF’ is not declared under prefix ‘inst’ for the line where the master agent is created.") – try to clean all build artefacts (ie reset all synthesis/design runs, or try to create a new project. If this doesn’t help, reinstall Vivado)
• Vivado hangs in an endless loop forever, e.g. after editing an IP or opening a source code file. You need to change the syntax checking engine from Sigasi to Vivado (Tools -> Settings -> Tool Settings -> Text Editor -> Syntax Checking -> Syntax checking).  More information: here

Seminar Presentations

9.11.	SoC Basics	ASIC vs FPGAs	Slides
16.11.	SoC Basics	The FPGA design process	Slides
23.11.	SoC Security	Reverse Engineering ICs	Slides
23.11.	SoC Security	Security Co-Processors	Slides
30.11.	SoC Security	FPGA Bitstream Encryption	Slides
7.12.	SoC Security	EM Side-Channel Attacks on SoCs
7.12.	SoC Security	Attacking FPGAs with covert channels	Slides
14.12.	SoC Security	Fault attacks on FPGAs	Slides
14.12.	SoC Security	Rowhammer Attacks on FPGAs	Slides
11.1.	SoC Environment	High Level Synthesis
11.1.	SoC Environment	Booting Linux

Material

• Introduction
• Seminar Topics
• Tutorial 1
• Tutorial 2
• Tutorial 3
• Project 1
• Project 2

Administrative Information

Previous Knowledge

This course addresses advanced-level students. Knowledge about software design, operating systems, networks, computer organization and digital design is necessary in order to be able to follow the course. There are no formal prerequisites.

Prerequisites Curriculum

See position in the curriculum

Objective

After having attended this course, the students have an understanding of current problems in designing complex embedded systems on silicon, also known as "systems on chip". The participants have gained insight into these by having studied typical microchip architectures and by modelling these. As a group, the participants will have designed and implemented a typical system.

Language

English

Teaching Method

The course material is defined through the course project`s problems. Each participant will specialize in a set of topics, and will present those topics to the whole group. With this knowledge, each group should be able to design, implement, and test the overall system.

How to get a grade

Grading consists of individual contributions throughout the course`s duration. In particular, these are one presentations, two exercises and active participation in discussions.

Registration

https://online.tugraz.at/tug_online/ee/rest/pages/slc.tm.cp/course-registration/336741

Lecturers