HDL Design Flow

The IAIK design flow is mainly based on Linux Makefiles. Makefiles can produce target files if one of its source files (dependency) changes. The design flow supports any language for high-level models. There exist several tools for mixed VHDL/Verilog designs.

HDL Simulation HDL simulation is performed using Cadence tools and TCL scripts. For both VHDL (ncvhdl) and Verilog (ncvlog) designs exist a simulator and graphical GUI (SimVision).
Hardware Synthesis For synthesis, we use the Encounter RTL Compiler from Cadence. The tool allows design optimizations in terms of time, area, and power.
Place and Route Logical cells are first placed in an integrated chip design. Second, the components are connected in a routing process. For that, we use the Cadence SOC Encounter tool. The output is an IC layout in GDS II (Graphic Database System) stream format.
Backend Verification For chip verification we use the Cadence Assura physical verification tool. It performs design rule checks, verifies the layout, and makes a transistor-based parasitic extraction. Layouts can be easily inspected by the Cadence Virtuoso Schematic Editor.
Power Simulation The power consumption of chip design can be simulated using Synopsys NanoSim. It performs a high accuracy transistor-level circuit simulation and reports power results of the design. .