LEON2-CIS
LEON2-CIS processor
LEON2-CIS is the name of an embedded processor with a configurable extended instruction set which is intended to facilitate processing of cryptographic algorithms (CIS = cryptography instruction set). It is based on the SPARC V8-compliant LEON2 processor maintained by Gaisler Research. LEON2-CIS has been developed in the course of the project ISEC ("Instruction-Set Extensions for Cryptography") at IAIK.
LEON2-CIS includes several custom instructions which aim at supporting both public-key and secret-key cryptographic algorithms. The following types of operations are supported:
- Modular arithmetic of long integers (for e.g. RSA, ECC over GF(p))
- Arithmetic in large binary extension fields (for e.g. ECC over GF(2m))
- Dedicated instructions for AES
Moreover, the LEON2-CIS features auxiliary functionality (e.g. a cycle counter), which might be of more general interest.
For further details on cryptographic instruction set extensions refer to our publications page.
The LEON2-CIS processor has been written to demonstrate a concrete application of the concept of instruction set extensions for cryptography and it is well suited for implementation in programmable logic devices (e.g., FPGAs). It is released to serve mainly for educational and research purposes. Please note that the CIS extensions have not been optimized for a specific FPGA or standard-cell technology and an implementation of LEON2-CIS may not make full use of all features of the technology at hand.
The HDL and supporting files of LEON2-CIS are available under the GNU LGPL, which is the same license as of the original LEON2 processor. The packages provide support for software development (extended GNU GCC and binutils toolchain), HDL simulation (ModelSim, NCSim) and synthesis (various standard-cell and FPGA technologies) and are available from the download page.