RSAb/RSAj High Speed RSA

Project Description

This project has been funded by the "Fonds zur Förderung der wissenschaftlichen Forschung" (Austrian Science Foundation) under projects P9384 and R12596-INF. The main goals of the project are centered around high speed implementations of public key cryptography. In particular, three research topics have been investigated: 1) the development of appropriate hardware algorithms, 2) the verification of these algorithms by using suitable methods for VLSI implementation, and 3) to design, manufacture, and test integrated circuits resulting from 1) and 2).

We initially have chosen two basic routes to achieve this, both similar in their general aim, but with different scales in time and speed. On the first route we have designed and implemented a series of RSA encryption/decryption chips with the goal of reaching an encryption speed of 200 kbits/sec. The second route has also the goal to propose a system for high speed public key cryptography, but with a different underlying arithmetic system, the residue number system. On this route, we have designed two chips which serve as the basic units in a massively parallel system.

An important goal of the project was to introduce state-of-the-art VLSI design methods and implementation techniques. Keywords here are hardware/software co-design, multi-level modelling, layout generators, dynamic logic, and design for testability.