Hardware Implementations of Cryptographic Algorithms

IAIK aims at the introduction of strong cryptographic algorithms in passive RFID tags. The main attacks against RFID systems cloning of tags, privacy violation, and the unallowed access to the tag's memory can be prevented when using cryptographic solutions. A main prerequisite for all security solutions is the ability to calculate a strong cryptographic algorithm on the tag.

Requirements

The fierce requirements of passive RFID systems where the tag draws the power from the electromagnetic field of the reader are the main challenge in implementing a strong cryptographic algorithm in hardware. The power consumption of the tag decides on the operating range of the tag. Hence, it is necessary to stay within the given limits. Also the chip area is of relevance because it determines the additional costs for the tag.

Achievements

IAIK implemented many different standardized crypto algorithms that have been optimized for application in passive RFID tags. All these algorithms are available as IP modules. Amongst others, the most interesting algorithms are AES-128, TEA, SHA-1, SHA-256, MD5, Grain, Trivium, ECC, and GPS. The following table shows die photographs of cryptp algorithm that have been manufactured in silicon.

AES-128 module (TINA) TINA stands for "tiny AES" and implements the Advanced Encryption Standard (AES) with 128-bit keys. The module has an 8-bit AMBA bus interface and is available as encryption-only and encryption-decryption module. The modules require a chip area around 3500 gate equivalents and have a mean current consumption below 3µA on a 0.35µm CMOS process technology with 1.5V supply voltage. The execution of encryption and decryption requires 1032 clock cycles.

Power-analysis protected AES-128 module (secureTINA) The secureTINA module is an extension of TINA that implements countermeasures against side-channel analysis. The implemented countermeasures use a combination of hiding and masking. In the time domain, randomization of operations is implemented. Additionally, the masked dual-rail prechargelogic style iMDPL is used for critical operations. The module requires a chip area of 20000 gate equivalents and has a power consumption of 15µA.

We offer our results of HW development activities as crypto IP modules. All modules are designed for application in systems with resource restricted requirements. Power and area efficient design achieving reasonable performance is the design principle we follow. All modules use quasi-standard SOC interfaces (e.g. AMBA bus) for easy integration. Visit our webstore for more detailed information about our hardware IP modules. You will find more information about AES implementations for passive RFID devices, AES modules for smart cards. Furthermore we offer hash modules computing SHA-1 and SHA-256 as well as various other algorithms that are not listed here.

For more information please contact: joern-marc.schmidt@iaik.tugraz.at