Attack Resistance and Tolerance Enabling Universal Security - ARTEUS

In recent times a special group of physical attacks against the implementation of embedded systems, so-called fault attacks, pose a serious threat to secure embedded systems. The basic idea of these attacks is to induce faults in a system by physically stressing it during sensitive operations. Maliciously induced faults can bypass security checks. In the context of cryptographic operations the faulty output of the device can be exploited to directly determine the secret key that is used by the system. Development of a methodology to deal with this sort of attacks during design and research towards effective countermeasures are the main goals of the ARTEUS. Within the project we are responsible for investigation of several aspects:

• Development of setups for invasive and semi-invasive fault attacks (optical and em based)
• Execution of attacks and evaluation of their impact
• Development of countermeasures on different levels of design cycle (error detection by coding theory, error detection on architecture level)
• Development of a methodology for design of protected circuits

The project ARTEUS started in February 2008 and is funded by the Austrian research programme FIT-IT. The originally planned project duration was 24 month, after a rather long startup phase we extended the project duration to 31 months. The project wil end in August 2010. The project partners are Infineon Technologies Austria and the Institute for Applied Information Processing and Communications from Graz University of Technology and Infineon Technologies AG Munich.

For more information please contact Jörn-Marc Schmidt.